1. Field of the Invention
The present invention relates to a multilayer wiring substrate in which a plurality of wirings, including via conductors and wiring conductors, is formed inside a substrate body.
2. Description of the Related Art
Hitherto, a multilayer wiring substrate has been used as a substrate on which a semiconductor element, such as an IC, is to be mounted. Outer terminals of the semiconductor element are arranged at a higher density with an increasing degree of integration. In view of such a situation, Patent Document 1 and Patent Document 2, given below, disclose multilayer wiring substrates each including a plurality of electrodes formed at a high density on an upper surface thereof on which a semiconductor element etc. are mounted. In those multilayer wiring substrates, a plurality of outer electrodes arranged at a relatively wide pitch is formed on a lower surface of the substrate. Those plural outer electrodes are electrically connected to the plural electrodes on the upper surface side through a plurality of wirings that are disposed inside the multilayer wiring substrate. Each of those wirings includes a plurality of via conductors disposed to penetrate through insulator layers of the multilayer wiring substrate, and a plurality of wiring conductors each electrically connecting the adjacent via conductors, which are disposed in the different insulator layers, at the interface between the insulator layers.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2008-300482
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2008-164577